Wafer inspection refers to inspecting semiconductor wafers for defects or abnormalities located on the surface of the wafer. Finding such defects is important for maximizing the production yield of integrated circuits (IC), where yield refers to the ratio of ICs that meet desired specifications to the total number of produced ICs. Maximizing yield is of outmost importance in semiconductor fabrication since yield determines the cost of an IC. Semiconductor fabrication comprises hundreds of intricate process steps that transform a bare semiconductor wafer into a number of ICs. Abnormalities or defects introduced in any of those process steps could result in a negative impact on yield. Therefore, semiconductor fabs employ wafer inspection tools to inspect wafers after each significant process step. Any abnormal increase in defects is immediately detected, reviewed, and analyzed to determine and eliminate the root cause of defects. In doing so, defects are prevented from propagating to multiple semiconductor wafers, leading to a containment of the negative impact on yield. Thus, yield is maximized by minimizing the negative impact of yield affecting defects.
However, maximizing yield is an increasingly challenging endeavor as the size of semiconductor nodes shrink. Shrinking of nodes, also called as node scaling, refers to the reduction in size of components of an IC with each next generation fabrication technology. Node scaling is the fundamental enabler for performance improvement (increased speed, reduced power, increased bandwidth, increased capacity) and cost reduction of ICs. Maintaining production yield as semiconductor fabrication inflects from one technology node to a next generation technology node is proving to be formidable challenge. This is primarily because of the inability of wafer inspection systems to improve at the same rate as node scaling. In the last ten years, while the smallest IC structures shrank from 130 nm to 14 nm (over 9× reduction), defect sensitivity of optical wafer inspection systems improved at a substantially slower rate from 50 nm to 20 nm (2.5× reduction). As a result, an increasing number of yield affecting defects pass undetected through wafer inspection systems, leading to a significant negative impact on yield.
Another reason for yield impact is because optical wafer inspection tools are designed primarily for detecting spherical particles, such as polystyrene latex (PSL) spheres or silicon dioxide (silica) spheres. The 50 nm to 20 nm improvement over the last decade corresponds to diameters of spherical particles. Remarkably, particles are only one of several defect types that can affect yield in semiconductor fabrication. Besides particles, defect types such as process induced defects, residues, crystalline originated particles, residues, and scratches can also cause a significant negative impact to production yield. The reason for the use of spherical particles is because light scattering from spherical particles can be easily modeled with techniques such as Mie scattering. As the shape of a defect deviates from a sphere, light scattering pattern of the defect also deviates from the light scattering pattern of a sphere. Therefore, an optical wafer inspection tool designed to maximize defect sensitivity for spherical particles may not be as sensitive for other defect shapes. For example, an optical wafer inspection tool specified to detect a 20 nm spherical particle may not be able to reliably detect a process induced defect having the same volume as the spherical particle. Unfortunately, such defects may pass completely undetected through wafer inspection systems, thereby having a negative impact on yield. Accordingly, there is a need for a method to certify the ability of a wafer inspection tool to detect diverse defects that could cause a negative impact on yield.
In a traditional wafer inspection procedure, optical wafer inspection is used for detecting the position and equivalent sizes of defects on wafers. If the number of defects, larger a predetermined defect size threshold, is higher than a predetermined defect count threshold value, defects on the wafer are considered to have the potential to affect yield. Such defects are reviewed with an electron microscope based defect review system. Reviewing refers to acquiring a high resolution image of a defect with an electron microscope. Since reviewing with an electron microscope is a very slow procedure compared to optical inspection, not all regions of the wafer are reviewed. To improve speed, the positions of defects captured with an optical inspection system are loaded into the electron microscope based review system, and high resolution images are captured only at those positions. While this shortcut improves speed, it simultaneously also opens up the possibility for defects not detected by optical wafer inspection system to pass through undetected in electron microscope based systems, even though the electron microscope based system has sufficient resolution to detect all yield affecting surface defects. Accordingly, there exists a stringent trade-off between speed of review and probability to capture defects.
Traditional wafer inspection suffers from the following problems: a) lack of a method to certify the ability of wafer inspection systems to detect diverse defect types; b) trade-off between speed of defect review and probability to capture defects.
Accordingly, there is a need for an improved wafer inspection method that can certify the ability of wafer inspection systems to detect diverse defect types; and relax the trade-off between speed of defect review and the probability to capture defects.